module alu_out(Q,D,CLK,RESET);

	input [31:0] D;
	input	CLK, RESET;
	output	[31:0] Q;
	reg	[31:0] Q;

	always@(posedge CLK or posedge RESET)
		begin
		if(RESET)
			begin
			Q <=32'd0;
			end
		else
			begin
			Q<=D;
			end
		end
endmodule
			
